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authorChris Wilson <chris@chris-wilson.co.uk>2010-12-14 12:29:23 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2010-12-14 12:29:23 +0100
commit71f4566084eb592fe545f05f7dff41fa9aa42e0b (patch)
tree0fc813df2af7ebda8dea06b6d954eb4cc5bbccfa /drivers/char
parentdrm/i915/sdvo: Only use the SDVO pin if it is in the valid range (diff)
downloadlinux-71f4566084eb592fe545f05f7dff41fa9aa42e0b.tar.xz
linux-71f4566084eb592fe545f05f7dff41fa9aa42e0b.zip
agp/intel: Fix missed cached memory flags setting in i965_write_entry()
This fixes regression from a6963596a13e62f8e65b1cf3403a330ff2db407c, that missed to set cached memory type in GTT entry. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-gtt.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 16a2847b7cdb..29ac6d499fa6 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1192,12 +1192,19 @@ static void i9xx_chipset_flush(void)
writel(1, intel_private.i9xx_flush_page);
}
-static void i965_write_entry(dma_addr_t addr, unsigned int entry,
+static void i965_write_entry(dma_addr_t addr,
+ unsigned int entry,
unsigned int flags)
{
+ u32 pte_flags;
+
+ pte_flags = I810_PTE_VALID;
+ if (flags == AGP_USER_CACHED_MEMORY)
+ pte_flags |= I830_PTE_SYSTEM_CACHED;
+
/* Shift high bits down */
addr |= (addr >> 28) & 0xf0;
- writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
+ writel(addr | pte_flags, intel_private.gtt + entry);
}
static bool gen6_check_flags(unsigned int flags)