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authorChris Wilson <chris@chris-wilson.co.uk>2010-12-22 15:04:47 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2011-01-11 21:35:41 +0100
commit55249baaa5cd188ebd9acdb047eeaed8092e4a93 (patch)
treeec52e1bdb516ce0bd259614b3c068960450b9236 /drivers/char
parentdrm/i915: Use the mappable sizes determined by GTT for consistency. (diff)
downloadlinux-55249baaa5cd188ebd9acdb047eeaed8092e4a93.tar.xz
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drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelines
On i830 if the tail pointer is set to within 2 cachelines of the end of the buffer, the chip may hang. So instead if the tail were to land in that location, we pad the end of the buffer with NOPs, and start again at the beginning. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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