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| author | Eric Anholt <eric@anholt.net> | 2009-11-03 00:33:05 +0100 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-02-26 22:23:18 +0100 |
| commit | e3deb204c69c485c88c990f07b71be10a464e508 (patch) | |
| tree | 6531d33bc519851b1cffabfc0cae19c7fc312d21 /drivers/char | |
| parent | drm/i915: Fix sandybridge status page setup. (diff) | |
| download | linux-e3deb204c69c485c88c990f07b71be10a464e508.tar.xz linux-e3deb204c69c485c88c990f07b71be10a464e508.zip | |
agp/intel: Use a non-reserved value for the cache field of the PTEs.
I don't know if this is what we'll want to be using long term, we'll see.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/char')
| -rw-r--r-- | drivers/char/agp/intel-agp.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index df85ed9c7531..c3c870bf5678 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -296,6 +296,11 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, off_t pg_start, int mask_type) { int i, j; + u32 cache_bits = 0; + + if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { + cache_bits = I830_PTE_SYSTEM_CACHED; + } for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { writel(agp_bridge->driver->mask_memory(agp_bridge, |