diff options
| author | Michel Dänzer <michel@tungstengraphics.com> | 2006-08-07 12:37:46 +0200 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2006-09-21 21:32:30 +0200 |
| commit | ae1b1a4816ac11075d338af79a239f4c326d675c (patch) | |
| tree | 60faac04eb4cf6d08b01d41e33dddd0f8275aad0 /drivers/char | |
| parent | drm: radeon: implement RADEON_PARAM_SCRATCH_OFFSET getparam (diff) | |
| download | linux-ae1b1a4816ac11075d338af79a239f4c326d675c.tar.xz linux-ae1b1a4816ac11075d338af79a239f4c326d675c.zip | |
drm: radeon: fix up bus mastering when writeback is disabled
When writeback isn't used, actually disable it in the hardware.
Not doing this might waste bus bandwidth or even cause memory corruption or
system crashes on systems that check bus transfers. No such incident has been
reported though.
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char')
| -rw-r--r-- | drivers/char/drm/radeon_cp.c | 7 | ||||
| -rw-r--r-- | drivers/char/drm/radeon_drv.h | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 5ad43ba7b5aa..3956628b2576 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c @@ -1258,6 +1258,13 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv) dev_priv->writeback_works = 0; DRM_INFO("writeback forced off\n"); } + + if (!dev_priv->writeback_works) { + /* Disable writeback to avoid unnecessary bus master transfer */ + RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | + RADEON_RB_NO_UPDATE); + RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); + } } /* Enable or disable PCI-E GART on the chip */ diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index e5a256f5429c..b54b8967dcd2 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h @@ -681,6 +681,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, #define RADEON_CP_RB_BASE 0x0700 #define RADEON_CP_RB_CNTL 0x0704 # define RADEON_BUF_SWAP_32BIT (2 << 16) +# define RADEON_RB_NO_UPDATE (1 << 27) #define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_WPTR 0x0714 |