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authorStephen Boyd <sboyd@kernel.org>2021-06-29 22:33:22 +0200
committerStephen Boyd <sboyd@kernel.org>2021-06-29 22:33:22 +0200
commit4f47c91fc6a8f4b274d934648b53cb668c69c986 (patch)
tree3d201c3b6865778d079151e288a6fa3b17fc823a /drivers/clk/Kconfig
parentMerge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk... (diff)
parentclk: lmk04832: Use of match table (diff)
parentclk: stm32mp1: new compatible for secure RCC support (diff)
parentclk: bd718xx: Drop BD70528 support (diff)
parentclk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC (diff)
parentclk: ingenic: Add support for the JZ4760 (diff)
downloadlinux-4f47c91fc6a8f4b274d934648b53cb668c69c986.tar.xz
linux-4f47c91fc6a8f4b274d934648b53cb668c69c986.zip
Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-ingenic' into clk-next
- Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs - Support secure mode of STM32MP1 SoCs - Improve clock support for Actions S500 SoC * clk-lmk04832: clk: lmk04832: Use of match table clk: lmk04832: Depend on SPI clk: lmk04832: add support for digital delay clk: add support for the lmk04832 dt-bindings: clock: add ti,lmk04832 bindings * clk-stm: clk: stm32mp1: new compatible for secure RCC support dt-bindings: clock: stm32mp1 new compatible for secure rcc dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 reset: stm32mp1: remove stm32mp1 reset clk: stm32mp1: move RCC reset controller into RCC clock driver clk: stm32mp1: convert to module driver clk: stm32mp1: remove intermediate pll clocks clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock * clk-rohm: clk: bd718xx: Drop BD70528 support * clk-actions: clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC clk: actions: Fix SD clocks factor table on Owl S500 SoC clk: actions: Fix UART clock dividers on Owl S500 SoC * clk-ingenic: clk: ingenic: Add support for the JZ4760 clk: ingenic: Support overriding PLLs M/N/OD calc algorithm clk: ingenic: Remove pll_info.no_bypass_bit clk: ingenic: Read bypass register only when there is one clk: Support bypassing dividers dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles