diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-10-11 13:27:16 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-10-27 03:27:43 +0200 |
| commit | 7029db09b2025f863f191b3d5b1d7859a5e26a8d (patch) | |
| tree | be34cc047ce7069e9c4d39c032cc469f760fd646 /drivers/clk/at91/at91sam9rl.c | |
| parent | clk: at91: clk-sam9x60-pll: add notifier for div part of PLL (diff) | |
| download | linux-7029db09b2025f863f191b3d5b1d7859a5e26a8d.tar.xz linux-7029db09b2025f863f191b3d5b1d7859a5e26a8d.zip | |
clk: at91: clk-master: add notifier for divider
SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
parent with cpuck as seen in the following clock tree:
+----------> cpuck
|
FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
while changing FRAC PLL or DIV PLL the commit implements a notifier for
mck0 which applies a safe divider to register (maximum value of the divider
which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
events.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/at91sam9rl.c')
| -rw-r--r-- | drivers/clk/at91/at91sam9rl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index ecbabf5162bd..4d4faf6c61d8 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) "masterck_pres", &at91rm9200_master_layout, &sam9rl_mck_characteristics, - &sam9rl_mck_lock, CLK_SET_RATE_GATE); + &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; |