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authorEric Anholt <eric@anholt.net>2016-02-16 04:03:58 +0100
committerMichael Turquette <mturquette@baylibre.com>2016-02-16 21:30:09 +0100
commit79c1e2fc2c0e0243d6ecaacfb650cf0ad5ad4aa5 (patch)
treec82e8c7ddf4730f820d335689602aceb13d6a8f5 /drivers/clk/bcm
parentclk: bcm2835: Fix setting of PLL divider clock rates (diff)
downloadlinux-79c1e2fc2c0e0243d6ecaacfb650cf0ad5ad4aa5.tar.xz
linux-79c1e2fc2c0e0243d6ecaacfb650cf0ad5ad4aa5.zip
clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()
We were rolling this ourselves, but clk-divider can do it now. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/bcm')
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 9f4df8f645f8..353e43835d5d 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1060,16 +1060,7 @@ static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
- struct bcm2835_cprman *cprman = divider->cprman;
- const struct bcm2835_pll_divider_data *data = divider->data;
- u32 div = cprman_read(cprman, data->a2w_reg);
-
- div &= (1 << A2W_PLL_DIV_BITS) - 1;
- if (div == 0)
- div = 256;
-
- return parent_rate / div;
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
}
static void bcm2835_pll_divider_off(struct clk_hw *hw)
@@ -1430,7 +1421,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
divider->div.reg = cprman->regs + data->a2w_reg;
divider->div.shift = A2W_PLL_DIV_SHIFT;
divider->div.width = A2W_PLL_DIV_BITS;
- divider->div.flags = 0;
+ divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
divider->div.lock = &cprman->regs_lock;
divider->div.hw.init = &init;
divider->div.table = NULL;