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| author | Robin Murphy <robin.murphy@arm.com> | 2020-06-18 19:56:29 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2020-07-08 16:22:10 +0200 |
| commit | 465931e70881476a210d44705102ef8b6ee6cdb0 (patch) | |
| tree | 9a200771c875d8e1a5caa7d6eb09130da9faa0e2 /drivers/clk/clk-cdce925.c | |
| parent | clk: rockchip: use separate compatibles for rk3288w-cru (diff) | |
| download | linux-465931e70881476a210d44705102ef8b6ee6cdb0.tar.xz linux-465931e70881476a210d44705102ef8b6ee6cdb0.zip | |
clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
This reverts commit 82f4b67f018c88a7cc9337f0067ed3d6ec352648.
According to a subsequent revert in the vendor kernel, the original
change was based on unclear documentation and was in fact incorrect.
Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a
phase where this had no impact, but limiting max-frequency to 150MHz to
match the nominal capability of the I/O pins made it virtually unusable,
constantly throwing errors and retuning. With this revert, it starts
behaving perfectly at 150MHz too.
Fixes: 82f4b67f018c ("clk: rockchip: fix wrong mmc sample phase shift for rk3328")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://lore.kernel.org/r/c80eb52e34c03f817586b6b7912fbd4e31be9079.1589475794.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/clk-cdce925.c')
0 files changed, 0 insertions, 0 deletions