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| author | Andrzej Hajda <a.hajda@samsung.com> | 2015-10-02 06:49:53 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-01-30 01:43:58 +0100 |
| commit | 090341b0a95d1f6d762915a75c13b393366f4ab3 (patch) | |
| tree | 2acd04488b4cdc85a9b38cbdc55ea48426efaf42 /drivers/clk/clk-divider.c | |
| parent | clk: add clk_unregister_fixed_rate() (diff) | |
| download | linux-090341b0a95d1f6d762915a75c13b393366f4ab3.tar.xz linux-090341b0a95d1f6d762915a75c13b393366f4ab3.zip | |
clk: vt8500: fix sign of possible PLL values
With unsigned values underflow in loops can occur resulting in
theoretically infinite loops.
The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-divider.c')
0 files changed, 0 insertions, 0 deletions