diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2015-07-24 21:21:12 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-07-28 20:59:28 +0200 |
| commit | 661e2180cf050a2f859d466f30d74e990b9345be (patch) | |
| tree | dee0ccf4613fa0fc115145eb144c02819e24e44b /drivers/clk/clk-fractional-divider.c | |
| parent | clk: qcom: Give clk-qcom.ko module a GPLv2 license (diff) | |
| download | linux-661e2180cf050a2f859d466f30d74e990b9345be.tar.xz linux-661e2180cf050a2f859d466f30d74e990b9345be.zip | |
clk: basic-type: Silence warnings about lock imbalances
The basic clock types use conditional locking for the register
accessor spinlocks. Add __acquire() and __release() markings in
the right locations so that sparse isn't tripped up on the
conditional locking.
drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block
drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block
drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-fractional-divider.c')
| -rw-r--r-- | drivers/clk/clk-fractional-divider.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 140eb5844dc4..e85f856b8592 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -27,11 +27,15 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, if (fd->lock) spin_lock_irqsave(fd->lock, flags); + else + __acquire(fd->lock); val = clk_readl(fd->reg); if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); + else + __release(fd->lock); m = (val & fd->mmask) >> fd->mshift; n = (val & fd->nmask) >> fd->nshift; @@ -80,6 +84,8 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, if (fd->lock) spin_lock_irqsave(fd->lock, flags); + else + __acquire(fd->lock); val = clk_readl(fd->reg); val &= ~(fd->mmask | fd->nmask); @@ -88,6 +94,8 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); + else + __release(fd->lock); return 0; } |