diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2016-06-17 12:51:07 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-08-16 00:39:32 +0200 |
| commit | 5a227cd1ab3693d36ac7a6f1fc4e21a7129f62f0 (patch) | |
| tree | d6bc84423880023bd60b3be346fdf1c8ce795fcb /drivers/clk/clk-max77686.c | |
| parent | clk: max77686: Add DT binding details for PMIC MAX77620 (diff) | |
| download | linux-5a227cd1ab3693d36ac7a6f1fc4e21a7129f62f0.tar.xz linux-5a227cd1ab3693d36ac7a6f1fc4e21a7129f62f0.zip | |
clk: max77686: Add support for MAX77620 clocks
Maxim Max77620 has one 32KHz clock output and the clock HW
IP used on this PMIC is same as what it is there in the MAX77686.
Add clock driver support for MAX77620 on the MAX77686 driver.
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-max77686.c')
| -rw-r--r-- | drivers/clk/clk-max77686.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 9aba3a8245e1..19f620856571 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -25,6 +25,7 @@ #include <linux/err.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/mfd/max77620.h> #include <linux/mfd/max77686.h> #include <linux/mfd/max77686-private.h> #include <linux/clk-provider.h> @@ -35,12 +36,14 @@ #include <dt-bindings/clock/maxim,max77686.h> #include <dt-bindings/clock/maxim,max77802.h> +#include <dt-bindings/clock/maxim,max77620.h> #define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3 enum max77686_chip_name { CHIP_MAX77686, CHIP_MAX77802, + CHIP_MAX77620, }; struct max77686_hw_clk_info { @@ -97,6 +100,15 @@ max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = { }, }; +static const struct +max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = { + [MAX77620_CLK_32K_OUT0] = { + .name = "32khz_out0", + .clk_reg = MAX77620_REG_CNFG1_32K, + .clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN, + }, +}; + static struct max77686_clk_init_data *to_max77686_clk_init_data( struct clk_hw *hw) { @@ -181,6 +193,11 @@ static int max77686_clk_probe(struct platform_device *pdev) hw_clks = max77802_hw_clks_info; break; + case CHIP_MAX77620: + num_clks = MAX77620_CLKS_NUM; + hw_clks = max77620_hw_clks_info; + break; + default: dev_err(dev, "Unknown Chip ID\n"); return -EINVAL; @@ -284,6 +301,7 @@ static int max77686_clk_remove(struct platform_device *pdev) static const struct platform_device_id max77686_clk_id[] = { { "max77686-clk", .driver_data = CHIP_MAX77686, }, { "max77802-clk", .driver_data = CHIP_MAX77802, }, + { "max77620-clock", .driver_data = CHIP_MAX77620, }, {}, }; MODULE_DEVICE_TABLE(platform, max77686_clk_id); |