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| author | Christian Marangi <ansuelsmth@gmail.com> | 2022-12-29 17:33:35 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-01-01 10:27:12 +0100 |
| commit | cfbd6de588ef659c198083205dc954a6d3ed2aec (patch) | |
| tree | 5c5239690ad4358838a87f8b2346b5249922892e /drivers/clk/clk-oxnas.c | |
| parent | Revert "net: dsa: qca8k: cache lo and hi for mdio write" (diff) | |
| download | linux-cfbd6de588ef659c198083205dc954a6d3ed2aec.tar.xz linux-cfbd6de588ef659c198083205dc954a6d3ed2aec.zip | |
net: dsa: qca8k: introduce single mii read/write lo/hi
It may be useful to read/write just the lo or hi half of a reg.
This is especially useful for phy poll with the use of mdio master.
The mdio master reg is composed by the first 16 bit related to setup and
the other half with the returned data or data to write.
Refactor the mii function to permit single mii read/write of lo or hi
half of the reg.
Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/clk/clk-oxnas.c')
0 files changed, 0 insertions, 0 deletions