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| author | Mark Kuo <mkuo@nvidia.com> | 2016-01-14 20:26:42 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-02-02 15:49:27 +0100 |
| commit | 442f53fb1be44c00263ebb8e7c2eff19dd019037 (patch) | |
| tree | c2b497f789c8f377d65a59a404a47bf4279b95f7 /drivers/clk/clk-pwm.c | |
| parent | clk: tegra: Fix typos around clearing PLLE bits during enable (diff) | |
| download | linux-442f53fb1be44c00263ebb8e7c2eff19dd019037.tar.xz linux-442f53fb1be44c00263ebb8e7c2eff19dd019037.zip | |
clk: tegra: Fix PLLE SS coefficients
The PLLE SS coefficients are different between Tegra210 and Tegra114.
Add SoC generation specific versions for Tegra114 and Tegra210 and use
them in their respective ->enable() callbacks.
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/clk-pwm.c')
0 files changed, 0 insertions, 0 deletions