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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-08-24 12:48:11 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-09-11 22:23:52 +0200 |
| commit | 6dcf03bcac31dec528867180f96580652fc3ac5b (patch) | |
| tree | 629c7cda441974b10a4424591726723c0a53867d /drivers/clk/clk-pwm.c | |
| parent | clk: vc3: Fix 64 by 64 division (diff) | |
| download | linux-6dcf03bcac31dec528867180f96580652fc3ac5b.tar.xz linux-6dcf03bcac31dec528867180f96580652fc3ac5b.zip | |
clk: vc3: Fix output clock mapping
According to Table 3. ("Output Source") in the 5P35023 datasheet,
the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3,
4=DIFF1, 5=DIFF2. But the code uses inverse. Fix this mapping issue.
Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@mail.gmail.com/
Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230824104812.147775-4-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-pwm.c')
0 files changed, 0 insertions, 0 deletions