diff options
| author | Marek Vasut <marek.vasut@gmail.com> | 2017-07-09 15:28:07 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-07-17 20:50:59 +0200 |
| commit | 3bded569cab4d839a47fcbd83e4e8926ae6ddad5 (patch) | |
| tree | 30fe34d02cc70aa9322fe89c1a79cabba01a0916 /drivers/clk/clk-versaclock5.c | |
| parent | clk: axs10x: introduce AXS10X pll driver (diff) | |
| download | linux-3bded569cab4d839a47fcbd83e4e8926ae6ddad5.tar.xz linux-3bded569cab4d839a47fcbd83e4e8926ae6ddad5.zip | |
clk: vc5: Prevent division by zero on unconfigured outputs
In case the initial values of the FOD registers are not configured in
the OTP or by the bootloader, it is possible that the FOD registers
will contain zeroes. The code in vc5_fod_recalc_rate() immediately
feeds the FOD divider value obtained from the FOD registers into the
div64_u64() and if the FOD divider value is zero, triggers division
by zero exception.
Check if the FOD divider value is zero and return the frequency of
the FOD output as 0 Hz if it is so. This prevents the division by
zero exception.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-versaclock5.c')
| -rw-r--r-- | drivers/clk/clk-versaclock5.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index ea7d552a2f2b..194d3f420847 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -426,6 +426,10 @@ static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | (od_frc[2] << 6) | (od_frc[3] >> 2); + /* Avoid division by zero if the output is not configured. */ + if (div_int == 0 && div_frc == 0) + return 0; + /* The PLL divider has 12 integer bits and 30 fractional bits */ return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); } |