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authorNicholas Mc Guire <hofrat@osadl.org>2016-12-12 08:40:09 +0100
committerStephen Boyd <sboyd@codeaurora.org>2017-01-10 01:06:41 +0100
commited784c532a3d0959db488f40a96c5127f63d42dc (patch)
treead2bc1ac6daaee970f48d998a8e0b0df58a3b5e6 /drivers/clk/clk-wm831x.c
parentclk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2 (diff)
downloadlinux-ed784c532a3d0959db488f40a96c5127f63d42dc.tar.xz
linux-ed784c532a3d0959db488f40a96c5127f63d42dc.zip
clk: wm831x: fix usleep_range with bad range
The delay here is not in atomic context and does not seem critical with respect to precision, but usleep_range(min,max) with min==max results in giving the timer subsystem no room to optimize uncritical delays. Fix this by setting the range to 2000,3000 us. Fixes: commit f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-wm831x.c')
-rw-r--r--drivers/clk/clk-wm831x.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 0621fbfb4beb..a47960aacfa5 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -97,7 +97,8 @@ static int wm831x_fll_prepare(struct clk_hw *hw)
if (ret != 0)
dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
- usleep_range(2000, 2000);
+ /* wait 2-3 ms for new frequency taking effect */
+ usleep_range(2000, 3000);
return ret;
}