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author | Stephen Boyd <sboyd@kernel.org> | 2019-07-12 20:11:51 +0200 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2019-07-12 20:11:51 +0200 |
commit | b1511f7a48c3ab28ae10b7ea1e9eae1481525bbe (patch) | |
tree | b8e66a9ce155841e4f8ee5f75b386fb83094bc1f /drivers/clk/clk.c | |
parent | Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', 'cl... (diff) | |
parent | clk: add BCM63XX gated clock controller driver (diff) | |
parent | clk: Add Si5341/Si5340 driver (diff) | |
parent | clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK (diff) | |
parent | Merge tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g... (diff) | |
download | linux-b1511f7a48c3ab28ae10b7ea1e9eae1481525bbe.tar.xz linux-b1511f7a48c3ab28ae10b7ea1e9eae1481525bbe.zip |
Merge branches 'clk-bcm63xx', 'clk-silabs', 'clk-lochnagar' and 'clk-rockchip' into clk-next
- Support gated clk controller on MIPS based BCM63XX SoCs
- Small frequency support for SiLabs Si544 chips
- Support SiLabs Si5341 and Si5340 chips
* clk-bcm63xx:
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
* clk-silabs:
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
* clk-lochnagar:
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: lochnagar: Use new parent_data approach to register clock parents
* clk-rockchip:
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
clk: rockchip: add a type from SGRF-controlled gate clocks
clk: rockchip: Remove 48 MHz PLL rate from rk3288
clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
clk: rockchip: Don't yell about bad mmc phases when getting
clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation