diff options
| author | David Lechner <david@lechnology.com> | 2018-05-25 20:11:47 +0200 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2018-05-30 21:48:35 +0200 |
| commit | 76c9dd9dbd6459f1faf2b10351eb3d3f90255fa1 (patch) | |
| tree | 48053e2359e7fe36ef488bdbf01a3429ba104964 /drivers/clk/davinci/pll-dm355.c | |
| parent | clk: davinci: psc-dm365: fix few clocks (diff) | |
| download | linux-76c9dd9dbd6459f1faf2b10351eb3d3f90255fa1.tar.xz linux-76c9dd9dbd6459f1faf2b10351eb3d3f90255fa1.zip | |
clk: davinci: pll: allow dev == NULL
This modifies the TI Davinci PLL clock driver to allow for the case
when dev == NULL. On some (most) SoCs that use this driver, the PLL
clock needs to be registered during early boot because it is used
for clocksource/clkevent and there will be no platform device available.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
Diffstat (limited to 'drivers/clk/davinci/pll-dm355.c')
| -rw-r--r-- | drivers/clk/davinci/pll-dm355.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c index 93f4a53d6b44..505aed80be9a 100644 --- a/drivers/clk/davinci/pll-dm355.c +++ b/drivers/clk/davinci/pll-dm355.c @@ -6,6 +6,7 @@ */ #include <linux/bitops.h> +#include <linux/clk/davinci.h> #include <linux/clkdev.h> #include <linux/init.h> #include <linux/types.h> @@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED) SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED); SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED); -int dm355_pll1_init(struct device *dev, void __iomem *base) +int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; - davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base); + davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc"); @@ -64,9 +65,9 @@ static const struct davinci_pll_clk_info dm355_pll2_info = { SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED); -int dm355_pll2_init(struct device *dev, void __iomem *base) +int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { - davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base); + davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip); davinci_pll_sysclk_register(dev, &pll2_sysclk1, base); |