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| author | Dinh Nguyen <dinguyen@altera.com> | 2014-02-19 22:11:11 +0100 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-02-26 21:23:40 +0100 |
| commit | b89cd950cbcd6a6aca37e82ecf369ab9909fdf24 (patch) | |
| tree | 711a1ada6d863af2fe3f8022d27820c7bd479a0e /drivers/clk/hisilicon/clk-hi3620.c | |
| parent | clk: socfpga: Fix integer overflow in clock calculation (diff) | |
| download | linux-b89cd950cbcd6a6aca37e82ecf369ab9909fdf24.tar.xz linux-b89cd950cbcd6a6aca37e82ecf369ab9909fdf24.zip | |
clk: socfpga: Support multiple parents for the pll clocks
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/hisilicon/clk-hi3620.c')
0 files changed, 0 insertions, 0 deletions