diff options
author | Herbert Xu <herbert@gondor.apana.org.au> | 2015-06-19 16:07:07 +0200 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2015-06-19 16:07:07 +0200 |
commit | c0b59fafe31bf91f589736be304d739b13952fdd (patch) | |
tree | 0088a41c6b68132739294643be06734e3af67677 /drivers/clk/hisilicon | |
parent | MAINTAINERS: clarify drivers/crypto/nx/ file ownership (diff) | |
parent | bus: mvebu-mbus: add mv_mbus_dram_info_nooverlap() (diff) | |
download | linux-c0b59fafe31bf91f589736be304d739b13952fdd.tar.xz linux-c0b59fafe31bf91f589736be304d739b13952fdd.zip |
Merge branch 'mvebu/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Merge the mvebu/drivers branch of the arm-soc tree which contains
just a single patch bfa1ce5f38938cc9e6c7f2d1011f88eba2b9e2b2 ("bus:
mvebu-mbus: add mv_mbus_dram_info_nooverlap()") that happens to be
a prerequisite of the new marvell/cesa crypto driver.
Diffstat (limited to 'drivers/clk/hisilicon')
-rw-r--r-- | drivers/clk/hisilicon/clk-hi3620.c | 70 | ||||
-rw-r--r-- | drivers/clk/hisilicon/clk-hix5hd2.c | 6 |
2 files changed, 38 insertions, 38 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 2e4f6d432beb..472dd2cb10b3 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -38,44 +38,44 @@ #include "clk.h" /* clock parent list */ -static const char *timer0_mux_p[] __initconst = { "osc32k", "timerclk01", }; -static const char *timer1_mux_p[] __initconst = { "osc32k", "timerclk01", }; -static const char *timer2_mux_p[] __initconst = { "osc32k", "timerclk23", }; -static const char *timer3_mux_p[] __initconst = { "osc32k", "timerclk23", }; -static const char *timer4_mux_p[] __initconst = { "osc32k", "timerclk45", }; -static const char *timer5_mux_p[] __initconst = { "osc32k", "timerclk45", }; -static const char *timer6_mux_p[] __initconst = { "osc32k", "timerclk67", }; -static const char *timer7_mux_p[] __initconst = { "osc32k", "timerclk67", }; -static const char *timer8_mux_p[] __initconst = { "osc32k", "timerclk89", }; -static const char *timer9_mux_p[] __initconst = { "osc32k", "timerclk89", }; -static const char *uart0_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *uart1_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *uart2_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *uart3_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *uart4_mux_p[] __initconst = { "osc26m", "pclk", }; -static const char *spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; -static const char *spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; -static const char *spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; +static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", }; +static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", }; +static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", }; +static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", }; +static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", }; +static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", }; +static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", }; +static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", }; +static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", }; +static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", }; +static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", }; +static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", }; +static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", }; +static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", }; +static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", }; +static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", }; +static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", }; +static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", }; /* share axi parent */ -static const char *saxi_mux_p[] __initconst = { "armpll3", "armpll2", }; -static const char *pwm0_mux_p[] __initconst = { "osc32k", "osc26m", }; -static const char *pwm1_mux_p[] __initconst = { "osc32k", "osc26m", }; -static const char *sd_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *mmc1_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", }; -static const char *g2d_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *venc_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *vdec_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *vpp_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *edc0_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *ldi0_mux_p[] __initconst = { "armpll2", "armpll4", +static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", }; +static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", }; +static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", }; +static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", }; +static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *edc1_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *ldi1_mux_p[] __initconst = { "armpll2", "armpll4", +static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *rclk_hsic_p[] __initconst = { "armpll3", "armpll2", }; -static const char *mmc2_mux_p[] __initconst = { "armpll2", "armpll3", }; -static const char *mmc3_mux_p[] __initconst = { "armpll2", "armpll3", }; +static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", }; +static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", }; /* fixed rate clocks */ diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c index 3f369c60fe56..f1d239435826 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -46,15 +46,15 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = { { HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, }, }; -static const char *sfc_mux_p[] __initconst = { +static const char *sfc_mux_p[] __initdata = { "24m", "150m", "200m", "100m", "75m", }; static u32 sfc_mux_table[] = {0, 4, 5, 6, 7}; -static const char *sdio_mux_p[] __initconst = { +static const char *sdio_mux_p[] __initdata = { "75m", "100m", "50m", "15m", }; static u32 sdio_mux_table[] = {0, 1, 2, 3}; -static const char *fephy_mux_p[] __initconst = { "25m", "125m"}; +static const char *fephy_mux_p[] __initdata = { "25m", "125m"}; static u32 fephy_mux_table[] = {0, 1}; |