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| author | Peng Fan <peng.fan@nxp.com> | 2020-05-07 07:56:12 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-05-20 03:26:42 +0200 |
| commit | dc6e21da340297604f217bcff016389cf78b2a49 (patch) | |
| tree | 3116e3232ff26b475573adc67db608e463ee9658 /drivers/clk/hisilicon | |
| parent | clk: imx8m: drop clk_hw_set_parent for A53 (diff) | |
| download | linux-dc6e21da340297604f217bcff016389cf78b2a49.tar.xz linux-dc6e21da340297604f217bcff016389cf78b2a49.zip | |
clk: imx: imx8mp: fix pll mux bit
Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll
driver for glitchless freq setting following spec. If exposing the
bit, that means pll driver and clk driver has two paths to touch
this bit, which is wrong.
So use EXT_BYPASS bit here.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/hisilicon')
0 files changed, 0 insertions, 0 deletions