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| author | Stephen Boyd <sboyd@kernel.org> | 2018-10-19 00:41:36 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-10-19 00:41:36 +0200 |
| commit | ffd3b1c880a9c5b5bfd977b4b33e61b6584ad943 (patch) | |
| tree | 5695b160eb6adf3ca3741c86f266d4ac0a231118 /drivers/clk/hisilicon | |
| parent | Merge branch 'clk-ti' into clk-next (diff) | |
| parent | Merge tag 'clk-v4.20-samsung' of git://git.kernel.org/pub/scm/linux/kernel/gi... (diff) | |
| parent | clk: hisilicon: Add clock driver for Hi3670 SoC (diff) | |
| parent | clk: at91: Fix division by zero in PLL recalc_rate() (diff) | |
| download | linux-ffd3b1c880a9c5b5bfd977b4b33e61b6584ad943.tar.xz linux-ffd3b1c880a9c5b5bfd977b4b33e61b6584ad943.zip | |
Merge branches 'clk-samsung', 'clk-hisi3670' and 'clk-at91-div-0' into clk-next
- Hisilicon 3670 SoC support
* clk-samsung:
dt-bindings: clock: samsung: Add SPDX license identifiers
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk: samsung: exynos5420: Enable PERIS clocks for suspend
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
clk: samsung: exynos4: Use generic helper for handling suspend/resume
clk: samsung: Add support for setting registers state before suspend
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
clk: samsung: Remove excessive include
* clk-hisi3670:
clk: hisilicon: Add clock driver for Hi3670 SoC
dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk
* clk-at91-div-0:
clk: at91: Fix division by zero in PLL recalc_rate()