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author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-08-10 17:14:33 +0200 |
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committer | Abel Vesa <abel.vesa@nxp.com> | 2021-08-24 15:09:07 +0200 |
commit | d36207b848a6490e14664e2197a1c8ab51d8148e (patch) | |
tree | d396817b32eed8c0c0a050edcdc2403a698648a4 /drivers/clk/imx/clk-composite-8m.c | |
parent | clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate (diff) | |
download | linux-d36207b848a6490e14664e2197a1c8ab51d8148e.tar.xz linux-d36207b848a6490e14664e2197a1c8ab51d8148e.zip |
clk: imx8m: fix clock tree update of TF-A managed clocks
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service
for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the
SiP and then does clk_set_parent on the DDR muxes to synchronize
the clock tree.
Since 936c383673b9 ("clk: imx: fix composite peripheral flags"),
these TF-A managed muxes have SET_PARENT_GATE set, which results
in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:
echo 25000000 > userspace/set_freq
imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set
dram_apb parent: -16
Fix this by adding a new i.MX composite flag for firmware managed
clocks, which clears SET_PARENT_GATE.
This is safe to do, because updating the Linux clock tree to reflect
reality will always be glitch-free.
Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'drivers/clk/imx/clk-composite-8m.c')
-rw-r--r-- | drivers/clk/imx/clk-composite-8m.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 2c309e3dc8e3..04e728538cef 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -216,7 +216,8 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, div->width = PCG_PREDIV_WIDTH; divider_ops = &imx8m_clk_composite_divider_ops; mux_ops = &clk_mux_ops; - flags |= CLK_SET_PARENT_GATE; + if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED)) + flags |= CLK_SET_PARENT_GATE; } div->lock = &imx_ccm_lock; |