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| author | Rongyi Chen <chenyi@tt-cool.com> | 2018-08-10 17:16:38 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2018-08-27 04:35:04 +0200 |
| commit | 58c0f79887d5e425fe6a9fd542778e50df69e9c6 (patch) | |
| tree | 6de7e85a2f62c31958b4f130647a5d84fc230200 /drivers/clk/imx/clk-imx35.c | |
| parent | clk: sunxi-ng: h6: fix bus clocks' divider position (diff) | |
| download | linux-58c0f79887d5e425fe6a9fd542778e50df69e9c6.tar.xz linux-58c0f79887d5e425fe6a9fd542778e50df69e9c6.zip | |
clk: sunxi-ng: h6: fix PWM gate/reset offset
Currently the register offset of the PWM bus gate in Allwinner H6 clock
driver is wrong.
Fix this issue.
Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Rongyi Chen <chenyi@tt-cool.com>
[Icenowy: refactor commit message]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk/imx/clk-imx35.c')
0 files changed, 0 insertions, 0 deletions