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authorPeng Fan <peng.fan@nxp.com>2019-07-15 04:55:43 +0200
committerShawn Guo <shawnguo@kernel.org>2019-08-03 09:16:04 +0200
commit053a4ffe298836bb973d2cba59f82fff60c7db5b (patch)
tree3425d393c52744573ab3f6195f286f374f7ce22f /drivers/clk/imx/clk-imx8mm.c
parentclk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m (diff)
downloadlinux-053a4ffe298836bb973d2cba59f82fff60c7db5b.tar.xz
linux-053a4ffe298836bb973d2cba59f82fff60c7db5b.zip
clk: imx: imx8mm: fix audio pll setting
The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Cc: <stable@vger.kernel.org> Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/imx/clk-imx8mm.c')
-rw-r--r--drivers/clk/imx/clk-imx8mm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index b914771e9878..359014dec0de 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -38,8 +38,8 @@ static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
};
static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = {
- PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
- PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
};
static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = {