diff options
| author | 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> | 2020-05-28 05:15:44 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-05-29 01:13:15 +0200 |
| commit | 9d9cc58aff468c1589df09ac12e4e79b1eaba6db (patch) | |
| tree | 80a1b469fa7564e180458cb9c6d732f9753441ae /drivers/clk/ingenic/jz4780-cgu.c | |
| parent | clk: Ingenic: Remove unnecessary spinlock when reading registers. (diff) | |
| download | linux-9d9cc58aff468c1589df09ac12e4e79b1eaba6db.tar.xz linux-9d9cc58aff468c1589df09ac12e4e79b1eaba6db.zip | |
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
The PLL of X1830 Soc from Ingenic has been greatly changed,
the bypass control is placed in another register, so now two
registers may needed to control the PLL. To this end, a new
"bypass_reg" was introduced. In addition, when calculating
rate, the PLL of X1830 introduced an extra 2x multiplier,
so a new "rate_multiplier" was introduced. And adjust the
code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/jz4780-cgu.c')
| -rw-r--r-- | drivers/clk/ingenic/jz4780-cgu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index c758f1643067..6c5b8029cc8a 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -13,6 +13,7 @@ #include <linux/of.h> #include <dt-bindings/clock/jz4780-cgu.h> + #include "cgu.h" #include "pm.h" @@ -266,6 +267,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { #define DEF_PLL(name) { \ .reg = CGU_REG_ ## name, \ + .rate_multiplier = 1, \ .m_shift = 19, \ .m_bits = 13, \ .m_offset = 1, \ @@ -277,6 +279,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { .od_max = 16, \ .od_encoding = pll_od_encoding, \ .stable_bit = 6, \ + .bypass_reg = CGU_REG_ ## name, \ .bypass_bit = 1, \ .enable_bit = 0, \ } |