diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2015-05-24 17:11:38 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-06-21 21:53:18 +0200 |
| commit | ed286ca5d627619673b7dad27f48252498e3905c (patch) | |
| tree | 57f3ea2b35095dff18f149a54474a2508cc5c897 /drivers/clk/ingenic | |
| parent | MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu (diff) | |
| download | linux-ed286ca5d627619673b7dad27f48252498e3905c.tar.xz linux-ed286ca5d627619673b7dad27f48252498e3905c.zip | |
MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu
The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions
there for such consistency.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10154/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/clk/ingenic')
| -rw-r--r-- | drivers/clk/ingenic/jz4740-cgu.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 0209ed6d412a..0e692ed632e5 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -26,6 +26,7 @@ #define CGU_REG_CPCCR 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 #define CGU_REG_SCR 0x24 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 @@ -47,6 +48,9 @@ /* bits within the LCR register */ #define LCR_SLEEP (1 << 0) +/* bits within the CLKGR register */ +#define CLKGR_UDC (1 << 11) + static struct ingenic_cgu *cgu; static const s8 pll_od_encoding[4] = { @@ -242,3 +246,21 @@ void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode) writel(lcr, cgu->base + CGU_REG_LCR); } + +void jz4740_clock_udc_disable_auto_suspend(void) +{ + uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); + + clkgr &= ~CLKGR_UDC; + writel(clkgr, cgu->base + CGU_REG_CLKGR); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend); + +void jz4740_clock_udc_enable_auto_suspend(void) +{ + uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); + + clkgr |= CLKGR_UDC; + writel(clkgr, cgu->base + CGU_REG_CLKGR); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend); |