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authorKelvin Cheung <keguang.zhang@gmail.com>2016-09-19 06:38:56 +0200
committerStephen Boyd <sboyd@codeaurora.org>2016-09-23 23:49:06 +0200
commitf0ffaf187addb5dcab76885fff9314b716fc8072 (patch)
treef3e6de93132dd0291fc5c3567b0ddb2ed0de921e /drivers/clk/loongson1
parentclk: Loongson1: Update clocks of Loongson1B (diff)
downloadlinux-f0ffaf187addb5dcab76885fff9314b716fc8072.tar.xz
linux-f0ffaf187addb5dcab76885fff9314b716fc8072.zip
clk: Loongson1: Make use of GENMASK
Make use of GENMASK instead of open coding the equivalent operation, and update the PLL formula. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/loongson1')
-rw-r--r--drivers/clk/loongson1/clk-loongson1b.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c
index 4b3d9d2983ee..f36a97e993c0 100644
--- a/drivers/clk/loongson1/clk-loongson1b.c
+++ b/drivers/clk/loongson1/clk-loongson1b.c
@@ -26,7 +26,7 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
u32 pll, rate;
pll = __raw_readl(LS1X_CLK_PLL_FREQ);
- rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
+ rate = 12 + (pll & GENMASK(5, 0));
rate *= OSC;
rate >>= 1;