diff options
| author | James Liao <jamesjj.liao@mediatek.com> | 2015-07-10 10:39:34 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-07-28 20:58:57 +0200 |
| commit | 75ce0cdb6243d42daca6130e5feb71f536bb136e (patch) | |
| tree | baa25bb3aceeb8638dc98938c02ddd9ae2470ebc /drivers/clk/mediatek/clk-mtk.h | |
| parent | clk: mediatek: Fix calculation of PLL rate settings (diff) | |
| download | linux-75ce0cdb6243d42daca6130e5feb71f536bb136e.tar.xz linux-75ce0cdb6243d42daca6130e5feb71f536bb136e.zip | |
clk: mediatek: Add MT8173 MMPLL change rate support
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting by adding
div-rate table to lookup suitable post divider setting under a
specified frequency.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 9dda9d8ad10b..efea28d6e1e6 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -134,6 +134,11 @@ struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); #define HAVE_RST_BAR BIT(0) +struct mtk_pll_div_table { + u32 div; + unsigned long freq; +}; + struct mtk_pll_data { int id; const char *name; @@ -150,6 +155,7 @@ struct mtk_pll_data { int pcwbits; uint32_t pcw_reg; int pcw_shift; + const struct mtk_pll_div_table *div_table; }; void __init mtk_clk_register_plls(struct device_node *node, |