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authorSascha Hauer <s.hauer@pengutronix.de>2015-04-23 10:35:40 +0200
committerStephen Boyd <sboyd@codeaurora.org>2015-05-06 07:50:33 +0200
commitd633fb7ac1e6abc39270edebbfa23131c673b5b9 (patch)
tree1054684c80836aab5786914e3bf13a10191e1dda /drivers/clk/mediatek/clk-mtk.h
parentclk: mediatek: Add initial common clock support for Mediatek SoCs. (diff)
downloadlinux-d633fb7ac1e6abc39270edebbfa23131c673b5b9.tar.xz
linux-d633fb7ac1e6abc39270edebbfa23131c673b5b9.zip
clk: mediatek: Add reset controller support
The pericfg and infracfg units also provide reset lines to several other SoC internal units. This adds a function which can be called from the pericfg and infracfg initialization functions which will register the reset controller using reset_controller_register. The reset controller will provide support for resetting the units connected to the pericfg and infracfg controller. The units resetted by this controller can use the standard reset device tree binding to gain access to the reset lines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.h')
-rw-r--r--drivers/clk/mediatek/clk-mtk.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 38f8ceb0470b..9dda9d8ad10b 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -156,4 +156,14 @@ void __init mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct clk_onecell_data *clk_data);
+#ifdef CONFIG_RESET_CONTROLLER
+void mtk_register_reset_controller(struct device_node *np,
+ unsigned int num_regs, int regofs);
+#else
+static inline void mtk_register_reset_controller(struct device_node *np,
+ unsigned int num_regs, int regofs)
+{
+}
+#endif
+
#endif /* __DRV_CLK_MTK_H */