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| author | Anson Huang <anson.huang@nxp.com> | 2019-04-26 08:53:14 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-05-03 18:31:54 +0200 |
| commit | a5a627c676590aaf381f38279ffdfacc963f18f4 (patch) | |
| tree | bb7509698434e652eaa78a2ab0190e10b71c853a /drivers/clk/mediatek | |
| parent | clk: imx: clk-pllv3: mark expected switch fall-throughs (diff) | |
| download | linux-a5a627c676590aaf381f38279ffdfacc963f18f4.tar.xz linux-a5a627c676590aaf381f38279ffdfacc963f18f4.zip | |
clk: imx: correct pfdv2 gate_bit/vld_bit operations
The operations of pfdv2 gate_bit/valid_bit are incorrect,
they are defined as u8 for bit offset, but gate_bit is
actually assigned as mask which could be 32 bit long and
it causes overflow, and vld_bit is assigned as bit offset
based on incorrect gate_bit value, it causes incorrect
pfd clock gate status in clock tree, this patch fixes the
issue by assigning them as correct bit offset.
Fixes: 9fcb6be3b6c9 ("clk: imx: add pfdv2 support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions