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authorRyder Lee <ryder.lee@mediatek.com>2018-04-17 14:30:27 +0200
committerStephen Boyd <sboyd@kernel.org>2018-05-16 00:17:49 +0200
commitbf61099a21f5a4da3b0551a88d7b3551fa4fff08 (patch)
tree7b38a09f9ea99c75d8c76fb1cb1008dbe599a791 /drivers/clk/mediatek
parentLinux 4.17-rc1 (diff)
downloadlinux-bf61099a21f5a4da3b0551a88d7b3551fa4fff08.tar.xz
linux-bf61099a21f5a4da3b0551a88d7b3551fa4fff08.zip
clk: mediatek: correct the clocks for MT2701 HDMI PHY module
The hdmitx_dig_cts clock signal is not a child of clk26m, and the actual output of the PLL block is derived from the tvdpll via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index deca7527f92f..4dda8988b2f0 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -46,8 +46,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
340 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
340 * MHZ),
- FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
- 300 * MHZ),
FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
27 * MHZ),
FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
@@ -977,6 +975,10 @@ static const struct mtk_pll_data apmixed_plls[] = {
21, 0x2d0, 4, 0x0, 0x2d4, 0),
};
+static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
+ FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
+};
+
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
@@ -988,6 +990,8 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
clk_data);
+ mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
+ clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
}