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authorRyder Lee <ryder.lee@mediatek.com>2018-12-05 07:41:10 +0100
committerStephen Boyd <sboyd@kernel.org>2018-12-05 21:30:30 +0100
commitd42925189b416b1559f3d74d663fa16c29942d96 (patch)
treef87f07b56a8a68ca0aa09420b391d087b7d11086 /drivers/clk/mediatek
parentclk: mediatek: Drop more __init markings for driver probe (diff)
downloadlinux-d42925189b416b1559f3d74d663fa16c29942d96.tar.xz
linux-d42925189b416b1559f3d74d663fa16c29942d96.zip
clk: mediatek: fix the PCIe MAC clock parent
The PCIe function doesn't work as the clock tree of MAC layer is wrong. Hence fix the clock table. Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
-rw-r--r--drivers/clk/mediatek/clk-mt7629.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 200ba147bbc6..d6233994af5a 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -446,8 +446,8 @@ static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
- FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
- FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
+ FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),
+ FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),
};
static const struct mtk_gate peri_clks[] = {