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authorStephen Boyd <sboyd@kernel.org>2019-03-08 19:29:30 +0100
committerStephen Boyd <sboyd@kernel.org>2019-03-08 19:29:30 +0100
commitefb1e0b07139974b506c90f4e0621d5866ee48b7 (patch)
tree2f320c3eefa309610aa1f6223f51ec682196f56c /drivers/clk/mediatek
parentMerge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ... (diff)
parentclk: ingenic: Remove set but not used variable 'enable' (diff)
parentclk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel (diff)
parentclk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks (diff)
parentclk: mediatek: Mark bus and DRAM related clocks as critical (diff)
parentclk: mediatek: correct cpu clock name for MT8173 SoC (diff)
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linux-efb1e0b07139974b506c90f4e0621d5866ee48b7.zip
Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next
* clk-ingenic: clk: ingenic: Remove set but not used variable 'enable' clk: ingenic: Fix doc of ingenic_cgu_div_info clk: ingenic: Fix round_rate misbehaving with non-integer dividers clk: ingenic: jz4740: Fix gating of UDC clock * clk-mtk-mux: clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 * clk-qcom-sdm845-pcie: clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks * clk-mtk-crit: clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro * clk-mtk: clk: mediatek: correct cpu clock name for MT8173 SoC