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| author | Yinbo Zhu <zhuyinbo@loongson.cn> | 2023-03-23 03:52:29 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-27 21:15:26 +0200 |
| commit | acc0ccffec502be0d64f477d4341957a897e4283 (patch) | |
| tree | 8829b4a195d6a1bd441c1273d8ed332c5940fc3f /drivers/clk/mediatek | |
| parent | dt-bindings: clock: add loongson-2 boot clock index (diff) | |
| download | linux-acc0ccffec502be0d64f477d4341957a897e4283.tar.xz linux-acc0ccffec502be0d64f477d4341957a897e4283.zip | |
clk: clk-loongson2: add clock controller driver support
This driver provides support for clock controller on Loongson-2 SoC,
the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock,
there are five independent PLLs inside, each of which PLL can
provide up to three sets of frequency dependent clock outputs.
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Link: https://lore.kernel.org/r/20230323025229.2971-2-zhuyinbo@loongson.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions