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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-09-27 12:11:27 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <wenst@chromium.org> | 2022-09-29 06:17:43 +0200 |
| commit | 341d2035fac07d710e1035f9922d97d96ddfa295 (patch) | |
| tree | 93cb36e531e74eeae8d83b40aa48a68c0dd19da3 /drivers/clk/mediatek | |
| parent | clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents (diff) | |
| download | linux-341d2035fac07d710e1035f9922d97d96ddfa295.tar.xz linux-341d2035fac07d710e1035f9922d97d96ddfa295.zip | |
clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
Following what was done on MT8183 and MT8195, also propagate the rate
changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-10-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8192-mfg.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c index 24108229793d..ec5b44ffa458 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -18,8 +18,10 @@ static const struct mtk_gate_regs mfg_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \ + _shift, &mtk_clk_gate_ops_setclr, \ + CLK_SET_RATE_PARENT) static const struct mtk_gate mfg_clks[] = { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0), |