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| author | Chen Zhong <chen.zhong@mediatek.com> | 2017-10-05 05:50:25 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-11-02 09:10:11 +0100 |
| commit | bda921fad518b4d5d2249d41432025ce5b368173 (patch) | |
| tree | dbe9fe429e88ed5ff37dec23aa70fa3f3bce0820 /drivers/clk/mediatek | |
| parent | clk: mediatek: add the option for determining PLL source clock (diff) | |
| download | linux-bda921fad518b4d5d2249d41432025ce5b368173.tar.xz linux-bda921fad518b4d5d2249d41432025ce5b368173.zip | |
clk: mediatek: add clocks dt-bindings required header for MT7622 SoC
Add the required header for the entire clocks dt-bindings exported
from topckgen, apmixedsys, infracfg, pericfg, ethsys, pciesys, ssusbsys
and audsys which could be found on MT7622 SoC.
Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions