diff options
| author | Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2021-09-14 04:16:13 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-09-15 00:05:37 +0200 |
| commit | 300796cad22153f63295a682b9f56f75e6227371 (patch) | |
| tree | 89fae9a3faf711a274b9b14d49524d2918fe919a /drivers/clk/mediatek | |
| parent | clk: mediatek: Fix corner case of tuner_en_reg (diff) | |
| download | linux-300796cad22153f63295a682b9f56f75e6227371.tar.xz linux-300796cad22153f63295a682b9f56f75e6227371.zip | |
clk: mediatek: Add API for clock resource recycle
In order to avoid resource leak when fail clock registration appears,
so adds the common interface to handle it.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-5-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.c | 9 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.h | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 4b6096c44d74..c3d385c0cfcb 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -43,6 +43,15 @@ err_out: return NULL; } +void mtk_free_clk_data(struct clk_onecell_data *clk_data) +{ + if (!clk_data) + return; + + kfree(clk_data->clks); + kfree(clk_data); +} + void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, struct clk_onecell_data *clk_data) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 7de41c3b3206..0ff289d93452 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, struct clk_onecell_data *clk_data); struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); +void mtk_free_clk_data(struct clk_onecell_data *clk_data); #define HAVE_RST_BAR BIT(0) #define PLL_AO BIT(1) |