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| author | Jerome Brunet <jbrunet@baylibre.com> | 2019-10-02 11:15:28 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2019-10-08 09:29:23 +0200 |
| commit | cf52db456fd02dc7a145a4f181c8490a1dfa26d9 (patch) | |
| tree | f39b1ae5b0ae07f3ae8601565b7bb8db4f337028 /drivers/clk/meson/axg-audio.h | |
| parent | clk: meson: axg-audio: prepare sm1 addition (diff) | |
| download | linux-cf52db456fd02dc7a145a4f181c8490a1dfa26d9.tar.xz linux-cf52db456fd02dc7a145a4f181c8490a1dfa26d9.zip | |
clk: meson: axg-audio: provide clk top signal name
The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.
On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg-audio.h')
| -rw-r--r-- | drivers/clk/meson/axg-audio.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h index c00e28b2e1a9..a4956837f597 100644 --- a/drivers/clk/meson/axg-audio.h +++ b/drivers/clk/meson/axg-audio.h @@ -116,9 +116,10 @@ #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 + /* include the CLKIDs which are part of the DT bindings */ #include <dt-bindings/clock/axg-audio-clkc.h> -#define NR_CLKS 163 +#define NR_CLKS 164 #endif /*__AXG_AUDIO_CLKC_H */ |