diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-01-19 16:42:36 +0100 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 09:49:23 +0100 |
| commit | 6c00e7b76021fcf4ddb64191ccdf62c722adf0d1 (patch) | |
| tree | 783c5d881ed9d73acbf63fb44eebc6bca9bd4b97 /drivers/clk/meson/clk-mpll.c | |
| parent | clk: meson: axg: fix the od shift of the sys_pll (diff) | |
| download | linux-6c00e7b76021fcf4ddb64191ccdf62c722adf0d1.tar.xz linux-6c00e7b76021fcf4ddb64191ccdf62c722adf0d1.zip | |
clk: meson: add axg misc bit to the mpll driver
On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
change (expect for mpll2 strangely). Looking at the vendor kernel, it
turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
is required.
Setting this bit solves the problem and the mpll rates are back to normal
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clk-mpll.c')
| -rw-r--r-- | drivers/clk/meson/clk-mpll.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index 5144360e2c80..6d79d6daadc4 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -173,6 +173,13 @@ static int mpll_set_rate(struct clk_hw *hw, reg = PARM_SET(p->width, p->shift, reg, n2); writel(reg, mpll->base + p->reg_off); + p = &mpll->misc; + if (p->width != 0) { + reg = readl(mpll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, 1); + writel(reg, mpll->base + p->reg_off); + } + if (mpll->lock) spin_unlock_irqrestore(mpll->lock, flags); else |