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authorLinus Torvalds <torvalds@linux-foundation.org>2019-06-28 02:50:09 +0200
committerLinus Torvalds <torvalds@linux-foundation.org>2019-06-28 02:50:09 +0200
commit556e2f6020bf90f63c5dd65e9a2254be6db3185b (patch)
tree2f4e23a47c8f8619bfc1deff4e180a6b48ff14a7 /drivers/clk/meson/g12a.h
parentMerge tag 'for-5.2/dm-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/g... (diff)
parentclk: socfpga: stratix10: fix divider entry for the emac clocks (diff)
downloadlinux-556e2f6020bf90f63c5dd65e9a2254be6db3185b.tar.xz
linux-556e2f6020bf90f63c5dd65e9a2254be6db3185b.zip
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A handful of clk driver fixes and one core framework fix - Do a DT/firmware lookup in clk_core_get() even when the DT index is a nonsensical value - Fix some clk data typos in the Amlogic DT headers/code - Avoid returning junk in the TI clk driver when an invalid clk is looked for - Fix dividers for the emac clks on Stratix10 SoCs - Fix default HDA rates on Tegra210 to correct distorted audio" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: socfpga: stratix10: fix divider entry for the emac clocks clk: Do a DT parent lookup even when index < 0 clk: tegra210: Fix default rates for HDA clocks clk: ti: clkctrl: Fix returning uninitialized data clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
Diffstat (limited to 'drivers/clk/meson/g12a.h')
-rw-r--r--drivers/clk/meson/g12a.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 39c41af70804..bcc05cd9882f 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -166,7 +166,7 @@
#define CLKID_HDMI_DIV 167
#define CLKID_MALI_0_DIV 170
#define CLKID_MALI_1_DIV 173
-#define CLKID_MPLL_5OM_DIV 176
+#define CLKID_MPLL_50M_DIV 176
#define CLKID_SYS_PLL_DIV16_EN 178
#define CLKID_SYS_PLL_DIV16 179
#define CLKID_CPU_CLK_DYN0_SEL 180