diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2017-08-01 13:56:59 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2017-08-04 18:02:02 +0200 |
| commit | 62ec0b9754aced0b4c02694886cbe9bfd3d00f2f (patch) | |
| tree | 8fda35ec7e8dcfd3f1d55cc405290a66b8e3a958 /drivers/clk/meson/gxbb-aoclk.c | |
| parent | clk: meson: gxbb-aoclk: Switch to regmap for register access (diff) | |
| download | linux-62ec0b9754aced0b4c02694886cbe9bfd3d00f2f.tar.xz linux-62ec0b9754aced0b4c02694886cbe9bfd3d00f2f.zip | |
clk: meson: gxbb-aoclk: Add CEC 32k clock
The CEC 32K AO Clock is a dual divider with dual counter to provide a more
precise 32768Hz clock for the CEC subsystem from the external xtal.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb-aoclk.c')
| -rw-r--r-- | drivers/clk/meson/gxbb-aoclk.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index f61506c53089..6c161e0a8e59 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -59,6 +59,7 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/init.h> +#include <linux/delay.h> #include <dt-bindings/clock/gxbb-aoclkc.h> #include <dt-bindings/reset/gxbb-aoclkc.h> #include "gxbb-aoclk.h" @@ -105,6 +106,17 @@ GXBB_AO_GATE(uart1, 3); GXBB_AO_GATE(uart2, 5); GXBB_AO_GATE(ir_blaster, 6); +static struct aoclk_cec_32k cec_32k_ao = { + .lock = &gxbb_aoclk_lock, + .hw.init = &(struct clk_init_data) { + .name = "cec_32k_ao", + .ops = &meson_aoclk_cec_32k_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_IGNORE_UNUSED, + }, +}; + static unsigned int gxbb_aoclk_reset[] = { [RESET_AO_REMOTE] = 16, [RESET_AO_I2C_MASTER] = 18, @@ -131,8 +143,9 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = { [CLKID_AO_UART1] = &uart1_ao.hw, [CLKID_AO_UART2] = &uart2_ao.hw, [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw, + [CLKID_AO_CEC_32K] = &cec_32k_ao.hw, }, - .num = ARRAY_SIZE(gxbb_aoclk_gate), + .num = 7, }; static int gxbb_aoclkc_probe(struct platform_device *pdev) @@ -172,6 +185,12 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev) return ret; } + /* Specific clocks */ + cec_32k_ao.regmap = regmap; + ret = devm_clk_hw_register(dev, &cec_32k_ao.hw); + if (ret) + return ret; + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, &gxbb_aoclk_onecell_data); } |