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authorJerome Brunet <jbrunet@baylibre.com>2018-07-04 18:54:58 +0200
committerJerome Brunet <jbrunet@baylibre.com>2018-07-09 13:49:31 +0200
commit7df533a7e3d2216e860ecf147ae8cee49bf133e9 (patch)
tree6a95385f018bca6963984ef1252fc3edc7f32ade /drivers/clk/meson/gxbb.h
parentclk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition (diff)
downloadlinux-7df533a7e3d2216e860ecf147ae8cee49bf133e9.tar.xz
linux-7df533a7e3d2216e860ecf147ae8cee49bf133e9.zip
clk: meson: add gen_clk
GEN_CLK is able to route several internal clocks to one of the SoC pads. In the future, even more clocks could be made accessible using cts_msr_clk - the clock measure block. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb.h')
-rw-r--r--drivers/clk/meson/gxbb.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index df6c21d368c6..20dfb1daf5b8 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -157,8 +157,10 @@
#define CLKID_VDEC_1_DIV 152
#define CLKID_VDEC_HEVC_SEL 154
#define CLKID_VDEC_HEVC_DIV 155
+#define CLKID_GEN_CLK_SEL 157
+#define CLKID_GEN_CLK_DIV 158
-#define NR_CLKS 157
+#define NR_CLKS 160
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>