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| author | Jerome Brunet <jbrunet@baylibre.com> | 2017-07-28 18:32:28 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2017-08-01 14:18:31 +0200 |
| commit | 1f737ffa13efd3da2c703d45894ea234e9290c89 (patch) | |
| tree | c7b8e973a1121f26b9f4f0f53277fac73ca5273c /drivers/clk/meson/meson8b.c | |
| parent | Linux v4.13-rc1 (diff) | |
| download | linux-1f737ffa13efd3da2c703d45894ea234e9290c89.tar.xz linux-1f737ffa13efd3da2c703d45894ea234e9290c89.zip | |
clk: meson: mpll: fix mpll0 fractional part ignored
mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider
Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/meson8b.c')
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index bb3f1de876b1..6ec512ad2598 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -267,6 +267,11 @@ static struct meson_clk_mpll meson8b_mpll0 = { .shift = 14, .width = 1, }, + .ssen = { + .reg_off = HHI_MPLL_CNTL, + .shift = 25, + .width = 1, + }, .lock = &clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll0", |