diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-03-24 16:11:03 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-04-01 13:34:09 +0200 |
| commit | b882964b376f214ef3d96d8a643c7c46121c30a8 (patch) | |
| tree | 6dc0ac81f09c913b586d06f28dc3a91cdfecbb35 /drivers/clk/meson/meson8b.h | |
| parent | clk: meson: meson8b: use a separate clock table for Meson8m2 (diff) | |
| download | linux-b882964b376f214ef3d96d8a643c7c46121c30a8.tar.xz linux-b882964b376f214ef3d96d8a643c7c46121c30a8.zip | |
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
Meson8m2 has a GP_PLL clock (similar to GP0_PLL on GXBB/GXL/GXM) which
is used as input for the VPU clocks.
The only supported frequency (based on Amlogic's vendor kernel sources)
is 364MHz which is achieved using the following parameters:
- input: XTAL (24MHz)
- M = 182
- N = 3
- OD = 2 ^ 2
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190324151104.18397-4-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/meson/meson8b.h')
| -rw-r--r-- | drivers/clk/meson/meson8b.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index b8c58faeae52..a45f7102c558 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -19,6 +19,7 @@ * * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf */ +#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ @@ -146,8 +147,10 @@ #define CLKID_MALI_1_SEL 178 #define CLKID_MALI_1_DIV 179 #define CLKID_MALI_1 180 +#define CLKID_GP_PLL_DCO 181 +#define CLKID_GP_PLL 182 -#define CLK_NR_CLKS 181 +#define CLK_NR_CLKS 183 /* * include the CLKID and RESETID that have |