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| author | Jerome Brunet <jbrunet@baylibre.com> | 2019-12-16 10:59:26 +0100 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2019-12-16 10:59:26 +0100 |
| commit | c97fcd8546c0c2a9e8e0512f501b1ca9aa25efdc (patch) | |
| tree | 462c23eae7f93f4e82347cfa497e39f1894cc478 /drivers/clk/meson | |
| parent | clk: meson: meson8b: use of_clk_hw_register to register the clocks (diff) | |
| parent | clk: meson: pll: Fix by 0 division in __pll_params_to_rate() (diff) | |
| download | linux-c97fcd8546c0c2a9e8e0512f501b1ca9aa25efdc.tar.xz linux-c97fcd8546c0c2a9e8e0512f501b1ca9aa25efdc.zip | |
Merge branch 'v5.5/fixes' into v5.6/drivers
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/clk-pll.c | 9 | ||||
| -rw-r--r-- | drivers/clk/meson/g12a.c | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index ddb1e5634739..3a5853ca98c6 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -77,6 +77,15 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, unsigned int m, n, frac; n = meson_parm_read(clk->map, &pll->n); + + /* + * On some HW, N is set to zero on init. This value is invalid as + * it would result in a division by zero. The rate can't be + * calculated in this case + */ + if (n == 0) + return 0; + m = meson_parm_read(clk->map, &pll->m); frac = MESON_PARM_APPLICABLE(&pll->frac) ? diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index b3af61cc6fb9..d2760a021301 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4692,6 +4692,7 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &g12a_bt656, &g12a_usb1_to_ddr, &g12a_mmc_pclk, + &g12a_uart2, &g12a_vpu_intr, &g12a_gic, &g12a_sd_emmc_a_clk0, |