diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2020-09-26 01:39:14 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-10-14 04:53:36 +0200 |
| commit | 07c565b42a04f38c49c3b09f89917cdf282c4743 (patch) | |
| tree | 140c474d58b213c652cb9d3f0d564d2bbc1c1bd4 /drivers/clk/mmp | |
| parent | Linux 5.9-rc1 (diff) | |
| download | linux-07c565b42a04f38c49c3b09f89917cdf282c4743.tar.xz linux-07c565b42a04f38c49c3b09f89917cdf282c4743.zip | |
clk: mmp2: Fix the display clock divider base
The LCD clock dividers are apparently based on one. No datasheet,
determined empirically, but seems to be confirmed by line 19 of lcd.fth in
OLPC laptop's Open Firmware [1]:
h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz
[1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mmp')
| -rw-r--r-- | drivers/clk/mmp/clk-of-mmp2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index 67208aea94c5..0839fb2049e9 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -347,9 +347,9 @@ static struct mmp_param_mux_clk mmp3_apmu_mux_clks[] = { }; static struct mmp_param_div_clk apmu_div_clks[] = { - {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock}, + {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock}, {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock}, - {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock}, + {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock}, {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock}, }; |