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authorStephen Boyd <sboyd@kernel.org>2020-10-20 20:47:02 +0200
committerStephen Boyd <sboyd@kernel.org>2020-10-20 20:47:02 +0200
commit97f2f490c1a46e5e2e80b5c423fe1f4e11b65ac1 (patch)
tree39530d077b0aca3a2e106ca0b28ef8a1c0227466 /drivers/clk/mmp
parentMerge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk... (diff)
parentclk: meson: use semicolons rather than commas to separate statements (diff)
parentclk: axi-clkgen: Set power bits for fractional mode (diff)
parentclk: qoriq: modify MAX_PLL_DIV to 32 (diff)
parentclk: baikal-t1: Mark Ethernet PLL as critical (diff)
parentclk: pxa: Constify static struct clk_ops (diff)
parentclk: mmp2: Fix the display clock divider base (diff)
downloadlinux-97f2f490c1a46e5e2e80b5c423fe1f4e11b65ac1.tar.xz
linux-97f2f490c1a46e5e2e80b5c423fe1f4e11b65ac1.zip
Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', 'clk-const' and 'clk-mmp2' into clk-next
* clk-semicolon: clk: meson: use semicolons rather than commas to separate statements clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements clk: uniphier: use semicolons rather than commas to separate statements * clk-axi-clkgen: clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers * clk-qoriq: clk: qoriq: modify MAX_PLL_DIV to 32 * clk-baikal: clk: baikal-t1: Mark Ethernet PLL as critical * clk-const: clk: pxa: Constify static struct clk_ops * clk-mmp2: clk: mmp2: Fix the display clock divider base