diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2020-03-09 20:42:42 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-03-21 02:19:31 +0100 |
| commit | ea56ad60260ec767d9a93f71f7baabcb618eb92d (patch) | |
| tree | 9a1bd58baed1c90613bc4d20fdda15fffee5b572 /drivers/clk/mmp | |
| parent | clk: mmp2: Add support for PLL clock sources (diff) | |
| download | linux-ea56ad60260ec767d9a93f71f7baabcb618eb92d.tar.xz linux-ea56ad60260ec767d9a93f71f7baabcb618eb92d.zip | |
clk: mmp2: Stop pretending PLL outputs are constant
The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly
off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default,
but also configurable.
Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various
values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and
set-pll2-988mhz Open Firmware words.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mmp')
| -rw-r--r-- | drivers/clk/mmp/clk-of-mmp2.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index ee086d971416..251d8d0e78ab 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -3,6 +3,7 @@ * * Copyright (C) 2012 Marvell * Chao Xie <xiechao.mail@gmail.com> + * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -55,7 +56,11 @@ #define APMU_CCIC1 0xf4 #define APMU_USBHSIC0 0xf8 #define APMU_USBHSIC1 0xfc + +#define MPMU_FCCR 0x8 +#define MPMU_POSR 0x10 #define MPMU_UART_PLL 0x14 +#define MPMU_PLL2_CR 0x34 struct mmp2_clk_unit { struct mmp_clk_unit unit; @@ -67,11 +72,14 @@ struct mmp2_clk_unit { static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { {MMP2_CLK_CLK32, "clk32", NULL, 0, 32768}, {MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000}, - {MMP2_CLK_PLL1, "pll1", NULL, 0, 800000000}, - {MMP2_CLK_PLL2, "pll2", NULL, 0, 960000000}, {MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000}, }; +static struct mmp_param_pll_clk pll_clks[] = { + {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0}, + {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10}, +}; + static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0}, {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0}, @@ -113,6 +121,10 @@ static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit) mmp_register_fixed_rate_clks(unit, fixed_rate_clks, ARRAY_SIZE(fixed_rate_clks)); + mmp_register_pll_clks(unit, pll_clks, + pxa_unit->mpmu_base, + ARRAY_SIZE(pll_clks)); + mmp_register_fixed_factor_clks(unit, fixed_factor_clks, ARRAY_SIZE(fixed_factor_clks)); |