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| author | Shawn Guo <shawn.guo@linaro.org> | 2013-03-26 14:22:55 +0100 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-04-01 10:30:04 +0200 |
| commit | 0c672aae287ef0b9a12a1ca67c1ad7a4bbe470ac (patch) | |
| tree | e70b2a021b7dfaaec8a9a54a6174ce0cd1681115 /drivers/clk/mxs/clk-imx28.c | |
| parent | clk: mxs: get base address from device tree (diff) | |
| download | linux-0c672aae287ef0b9a12a1ca67c1ad7a4bbe470ac.tar.xz linux-0c672aae287ef0b9a12a1ca67c1ad7a4bbe470ac.zip | |
clk: mxs: remove the use of mach level IO accessor
It removes the use of mach level IO accessor __mxs_setl/clrl, and hence
removes mach header inclusion from clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/mxs/clk-imx28.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index f623fdd93b46..d0e5eed146de 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -16,7 +16,6 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <mach/mx28.h> #include "clk.h" static void __iomem *clkctrl; @@ -75,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux) if (clkmux > 0x3) return -EINVAL; - __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL); - __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL); + writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); + writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); return 0; } @@ -86,13 +85,13 @@ static void __init clk_misc_init(void) u32 val; /* Gate off cpu clock in WFI for power saving */ - __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); + writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); /* 0 is a bad default value for a divider */ - __mxs_setl(1 << BP_ENET_DIV_TIME, ENET); + writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); /* Clear BYPASS for SAIF */ - __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ); + writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); /* SAIF has to use frac div for functional operation */ val = readl_relaxed(SAIF0); @@ -112,7 +111,7 @@ static void __init clk_misc_init(void) * Source ssp clock from ref_io than ref_xtal, * as ref_xtal only provides 24 MHz as maximum. */ - __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ); + writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); /* * 480 MHz seems too high to be ssp clock source directly, |